Japanese Patent Laid-Open No. 2003-051989 describes a method of amplifying, by a gain amplifier 41 in each column, signals output from the pixels in the column in a pixel array in which a plurality of pixels are two-dimensionally arrayed. When a MOS switch 54 is ON, the gain amplifier 41 operates as a voltage follower to initialize an inverting input portion 48. A pulse synchronous with that applied to a supply terminal 45 is applied to a supply terminal 58 to match the potential of an output portion 51 with the one obtained by adding the offset voltage of the gain amplifier 41 to the potential of a non-inverting input portion 47, thereby storing the offset of the gain amplifier 41 in a capacitance 23. A pulse applied to a pulse terminal 14 is set to high level to transfer an optical signal generated by a photodiode 2 to the gate of a MOS transistor 3 via a transfer MOS transistor 4. Note that a noise signal generated upon resetting the potential of a pixel 1 is superimposed on the optical signal transferred to the gate of the MOS transistor 3. When a pulse at high level is continuously applied to a pulse supply terminal 38, an amplification signal based on the optical signal on which the noise signal is superimposed is input to the gain amplifier 41. At this time, the MOS switch 54 is OFF, so the gain amplifier 41 operates as a voltage feedback operational amplifier (op amp) to amplify the input signal by the gain determined by the ratio of capacitances 55 and 56. Therefore, a signal obtained by superimposing the offset level of the gain amplifier 41 on the signal output from the gain amplifier 41 is stored in a capacitance 24. Letting C1 and C2 be the values of the capacitances 55 and 56, respectively, the gain is (C1+C2)/C2. When a horizontal scanning circuit 34 is driven, pulse signals output to a first column selection output line 35-1 and second column selection output line 35-2 sequentially become high level. The signals stored in the capacitances 23 and 24 are respectively output to horizontal output lines 27 and 28 via MOS transistors 29 and 30. The respective signals guided to the horizontal output lines 27 and 28 are input to a differential amplifier 39, where their difference is calculated, and an amplification signal based on the optical signal is output from an output terminal 40. According to Japanese Patent Laid-Open No. 2003-051989, the differential amplifier 39 eliminates the offset of the gain amplifier 41 with the foregoing operation.
In recent years, image capturing devices are increasingly required to attain higher performances, so increasing the number of pixels is a challenge of paramount importance in developing these devices. Any attempt to increase the number of pixels in image capturing devices inevitably results in a reduction in pixel size. A general image capturing device includes readout circuits corresponding to respective columns, and this makes it necessary to decrease the pitches of readout circuits with a reduced pixel size as well.
The inventor of the present invention found that a current mainstream image capturing device with a pixel pitch of about 1 μm to 3 μm has too low a level to allow a differential amplifier to sufficiently eliminate the offset of a gain amplifier. If the differential amplifier cannot sufficiently eliminate the offset of the gain amplifier, an image signal in which fixed pattern noise remains is output, and this leads to deterioration in quality of an image obtained based on that image signal.
Also, when a subsequent stage of an image capturing device eliminates the offset of a gain amplifier, it may not be sufficiently eliminated if the offset level of the gain amplifier is relatively high. In this case as well, an image in which fixed pattern noise remains is output, and this leads to deterioration in quality of an image obtained based on that image signal.